Microprocessor-accessible memory devices have traditionally been classified as either non-volatile or volatile memory devices. Non-volatile memory devices are capable of retaining stored information even when power to the memory device is turned off. Traditionally, however, non-volatile memory devices occupy a large amount of space and consume large quantities of power, making these devices unsuitable for use in portable devices or as substitutes for frequently-accessed volatile memory devices. On the other hand, volatile memory devices tend to provide greater storage capability and programming options than non-volatile memory devices. Volatile memory devices also generally consume less power than non-volatile devices. However, volatile memory devices require a continuous power supply in order to retain stored memory content.
Research and development of commercially viable memory devices that are randomly accessed, have relatively low power consumption, and are non-volatile is ongoing. One ongoing area of research is in resistive memory cells where resistance states can be programmably changed. One avenue of research relates to devices that store data in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied programming voltages, which in turn change cell resistance. Examples of variable resistance memory devices being investigated include memories using variable resistance polymers, perovskite, doped amorphous silicon, phase-changing glasses, and doped chalcogenide glass, among others.
FIG. 1 shows a basic composition of a typical variable resistance memory cell such as a phase change memory cell 10 constructed over a substrate 12, having a variable resistance material, e.g., a phase change material 16 formed between a bottom electrode 14 and a top electrode 18. One type of variable resistance material may be amorphous silicon doped with V, Co, Ni, Pd, Fe and Mn as disclosed in U.S. Pat. No. 5,541,869 to Rose et al. Another type of variable resistance material may include perovskite materials such as Pr(1-x)CaxMnO3 (PCMO), La(1-x)CaxMnO3 (LCMO), LaSrMnO3 (LSMO), GdBaCoxOy), (GBCO) as disclosed in U.S. Pat. No. 6,473,332 to Ignatiev et al. Still another type of variable resistance material may be a doped chalcogenide glass of the formula AxBy, where “B” is selected from among S, Se and Te and mixtures thereof, and where “A” includes at least one element from Group III-A (B, Al, Ga, In, TI), Group IV-A (C, Si, Ge, Sn, Pb), Group V-A (N, P, As, Sb, Bi), or Group VII-A (F, Cl, Br, I, At) of the periodic table, and with the dopant being selected from among the noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni, as disclosed in U.S. Pat. Nos. 6,881,623 and 6,888,155 to Campbell et al. and Campbell, respectively. Yet another type of variable resistance material includes a carbon-polymer film comprising carbon black particulates or graphite, for example, mixed into a plastic polymer, such as that disclosed in U.S. Patent No. 6,072,716 to Jacobson et al. The material used to form the electrodes 14, 18 can be selected from a variety of conductive materials, such as tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among others.
Much research has focused on memory devices using memory elements composed of chalcogenides. Chalcogenides are alloys of Group VI elements of the periodic table, such as Te or Se. A specific chalcogenide currently used in rewriteable compact discs (“CD-RWs”) is Ge2Sb2Te5. In addition to having valuable optical properties that are utilized in CD-RW discs, Ge2Sb2Te5 also has desirable physical properties as a variable resistance material. Various combinations of Ge, Sb and Te may be used as variable resistance materials and which are herein collectively referred to as GST materials. Specifically, GSTs can change structural phases between an amorphous phase and two crystalline phases. The resistance of the amorphous phase (“a-GST”) and the resistances of the cubic and hexagonal crystalline phases (“c-GST” and “h-GST,” respectively) can differ significantly. The resistance of amorphous GST is greater than the resistances of either cubic GST or hexagonal GST, whose resistances are similar to each other. Thus, in comparing the resistances of the various phases of GST, GST may be considered a two-state material (amorphous GST and crystalline GST), with each state having a different resistance that can be equated with a corresponding binary state. A variable resistance material such as GST whose resistance changes according to its material phase is referred to as a phase change material.
The transition from one GST phase to another occurs in response to temperature changes of the GST material. The temperature changes, i.e., the heating and cooling, can be caused by passing differing amounts of current through the GST material. The GST material is placed in a crystalline state by passing a crystallizing current through the GST material, thus warming the GST material to a temperature wherein a crystalline structure may grow. A stronger melting current is used to melt the GST material for subsequent cooling to an amorphous state. As the typical phase change memory cell uses the crystalline state to represent one logical state binary, e.g., “1,” and the amorphous state to represent another logical state binary, e.g., “0,” the crystallizing current is referred to as a set current ‘SET and the melting current is referred to as an erase or reset current IRST. One skilled in the art will understand, however, that the assignment of GST states to binary values may be switched if desired. The set currents ISET and the erase or reset currents IRST are typically large, often in the order of a few hundred microamps.
A typical resistive memory bit structure such as a phase change memory bit structure 315 that incorporates a phase change memory cell 10, for example, is represented schematically in FIG. 2A. In FIG. 2A, the memory cell 10 is connected to a cell select line 320 via either the cell's top or bottom electrode. The opposing electrode is connected to an access device 350 such as an access transistor. The access device 350 is gated by a word line 330. A bit line 340 provides a source to the access device 350 and is connected to the memory cell 10 when the access device 350 is activated by the word line 330. The access device 350 must be sufficiently large in order to pass the large phase changing currents ISET and IRST to the memory cell 10.
The memory bit structure 315 of FIG. 2A may be arranged into an array of memory bit structures, as illustrated in FIG. 2B. In FIG. 2B, a conventional resistive memory device 400 includes an array of memory bit structures 315a-315h. The memory bit structures 315a-315h are arranged in rows and columns. The rows and columns may be partially staggered, as in FIG. 2B, or may be aligned in parallel. The memory bit structures 315a-315h along any given cell select line 320a-320d do not share a common word line 330a-330d. Additionally, the memory bit structures 315a-315h along any given word line 330a-330d do not share a common bit line 340a-340d. In this manner, each memory bit structure is uniquely identified by the combined selection of the word line to which the gate of the memory cell access device 350a-350h is connected, and the cell select line to which the memory cell is connected.
Each word line 330a-330d is connected to a word line driver in the form of a row decoder 460 for selecting the respective word line for an access operation. Similarly, each cell select line 320a-320d is coupled to a driver in the form of a column decoder 450.
For simplicity, FIG. 2B illustrates a memory array having only four rows of memory bit structures 315 on four cell select lines 320a-320d and four columns of memory bit structures 315 on four word lines 330a-330d. However, it should be understood that in practical applications, the memory device 400 has significantly more memory bit structures in an array. For example, an actual memory device may include several million memory bit structures 315 arranged in a number of subarrays.
Significantly, FIGS. 2A and 2B illustrate how each memory cell 10 is connected to a separate and individual access device 350. As was described above, in resistive memory cells such as the phase change memory cells 10, the amount of current necessary to change at least a portion of the phase change material 16 into an amorphous state is relatively high (generally a few hundred microamps). As a result, the access device 350 for each memory cell 10 is correspondingly large. In a conventional phase change memory bit structure with a one-to-one correspondence between memory cells and access devices, the typical memory bit area is 16 F2, meaning an area equal to 16 F2, where F is the fabrication resolution. Because of continued desire to reduce the overall footprint of memory bit structures, there is a need to reduce the footprint of resistive memory bit structures, e.g., phase change memory bit structures.